Renesas Electronics /R7FA6M3AH /GLCDC /TCON_TIM

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Interpret as TCON_TIM

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OFFSET)OFFSET0 (HALF)HALF

OFFSET=OFFSET, HALF=HALF

Description

TCON Reference Timing Setting Register

Fields

OFFSET

Horizontal synchronization signal generation reference timingSets the offset from the assertion of the internal horizontal synchronization signal in terms of pixels.

0 (OFFSET): OFFSET+1 pixels. The valid range is 0x000 to 0x3FF.

HALF

Vertical synchronization signal generation change timing Sets the delay from the assertion of the internal horizontal synchronization signal in terms of pixels.

0 (HALF): HALF pixels. The valid range is 0x000 to 0x3FF.

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